1. Field of the Invention
The present invention relates generally to charge pump circuits, and more particularly but not exclusively to methods and apparatus for regulating the output current for a charge pump circuit.
2. Description of the Background Art
A typical PLL (phase lock loop) comprises a PFD (phase/frequency detector), a charge pump circuit, a loop filter, and a VCO (voltage controlled oscillator). The PFD compares the phase of a reference clock with that of the output clock of the VCO. Usually two logical signals, said UP and DN signals are used by the PFD to represent the phase difference between the two clocks. Each time a phase comparison is made, an UP pulse and a DN pulse are generated. If the reference clock is leading the VCO output clock (in clock phase), the UP pulse is longer than the DN pulse. Otherwise, the DN pulse is longer than the UP pulse. The two logical signals are converted into a current signal using the charge pump circuit. FIG. 1 schematically depicts a prior art charge pump circuit. Throughout this disclosure, VDD denotes a supply voltage. The charge pump circuit comprises a current source 110 of magnitude I, a switch 120 controlled by the UP signal, a current sink 130 of magnitude I, and a switch 140 controlled by the DN signal. When UP is 1 and DN is 0, the output current IOUT is positive (i.e. out-flowing). When UP is 0 and DN is 1, the output current IOUT is negative (i.e. in-flowing). When UP is 0 and DN is 0, or UP is 1 and DN is 1, the output current IOUT is zero. The output of the charge pump is connected to the loop filter, which typically comprises a resistor in series with a capacitor to convert the output current from the charge pump into a voltage, which is used to control the VCO.
In practice, however, the prior art charge pump circuits shown in FIG. 1 are prone to problems due to circuit non-idealities. First, the magnitude of the current source 110 may not be exactly the same as that of the current sink 130 due to variation within the manufacturing process. Second, a practical current source/sink always has finite output impedance, and therefore the output current is always load-dependent.
FIG. 2 schematically shows an equivalent circuit of the charge pump circuit depicted in FIG. 1 in practical conditions. The current source 110 in FIG. 1 is replaced by a practical current source 250 comprising an ideal current source 210 of magnitude I1 in parallel with a resistor R1. The current sink 130 in FIG. 1 is replaced by a practical current sink 260 comprising an ideal current sink 230 of magnitude I2 in parallel with a resistor R2. As a result, there is a mismatch between the current source and the current sink, and also the mismatch is load-dependent. When the output voltage at the load increases/decreases, the current flowing out of the practical current source 250 will decrease/increase, while the current flowing into the practical current sink 260 will increase/decrease. Therefore, even if I1 is made exactly the same as I2, there is still a load-dependent mismatch between the current source 250 and the current sink 260. The mismatch between the current source and the current sink usually results in appreciable degradation to the PLL performance, most noticeably in causing spurious frequency components.
Prior arts rely on circuit design techniques to guarantee a good matching between the current source and the current sink, and also a high output resistance for both the current source and the current sink. In a CMOS integrated circuit implementation, for example, people may use large transistors to assure good matching. A good matching is thus achieved at the cost of increased circuit area. Also, people may use a “cascode” topology by stacking up transistors to achieve a high output resistance when implementing a current source/sink. A high output resistance is thus achieved at the cost of reduced output voltage range.
What is needed is an improved charge pump circuit that is self-regulated so that the current source and current sink match well regardless of voltage at the load without sacrificing much output voltage range.